MODE10BIT=DISABLE_THE_10_BIT_C, LPWRMODE=DISABLE_THE_LOW_POWE, EDGE=RISING, START=NO_START_THIS_VALUE, BURST=SOFTWARE_CONTROLLED_
A/D Control Register. The CR register must be written to select the operating mode before A/D conversion can occur.
| SEL | Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,…, and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01). |
| CLKDIV | The main clock (PCLK_ADC) is divided by (this value plus one) to produce the clock for the A/D converter. The clock should be less than or equal to 15.5 MHz(12-bit mode) or 31 MHz (10-bit mode) in software-controlled mode (BURST bit = 0)… Typically, software should program the smallest value in this field that yields a clock of 15.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. |
| BURST | Burst mode If BURST is set to 1, the ADGINTEN bit in the INTEN register (Table 327) must be set to 0. 0 (SOFTWARE_CONTROLLED_): Software-controlled mode: Conversions are software-controlled and require 31 clocks. 1 (HARDWARE_SCAN_MODE_): Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by ones in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher bits (pins) set to one are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1, or conversions will not start. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |
| LPWRMODE | Low-power mode 0 (DISABLE_THE_LOW_POWE): Disable the low-power ADC mode. The analog circuitry remains activated when no conversions are requested. 1 (ENABLE_THE_LOW_POWER): Enable the low-power ADC mode. The analog circuitry is automatically powered-down when no conversions are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is enabled. After the required start-up time, the requested conversion will be launched. Once the conversion completes, the analog-circuitry will again be powered-down provided no further conversions are pending. This mode will NOT power-up the A/D if the ADC is powered down (ADC_PD bit in the PDRUNCFG register is HIGH) or if the part is in Deep-sleep, Power-down, or Deep power-down mode. |
| MODE10BIT | 10-bit conversion rate mode 0 (DISABLE_THE_10_BIT_C): Disable the 10-bit conversion rate mode. 1 (ENABLE_THE_10_BIT_CO): Enable the 10-bit conversion rate mode with high conversion rate.The A/D resolution is reduced to 10 bits (the two LSB of the conversion result will be forced to 0). The clock rate (set via the CLKDIV field) can be doubled to up to 31 MHz to achieve a conversion rate of up to one million samples per second. |
| START | When the BURST bit is 0, these bits control whether and when an A/D conversion is started: 0 (NO_START_THIS_VALUE): No start (this value should be used when clearing PDN to 0). 1 (START_CONVERSION_NOW): Start conversion now. 2 (PIO0_2): Start conversion when the edge selected by bit 27 occurs on PIO0_2/SSEL/CT16B0_CAP0. 3 (PIO1_5): Start conversion when the edge selected by bit 27 occurs on PIO1_5/DIR/CT32B0_CAP0. 4 (CT32B0_MAT0): Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0[1]. 5 (CT32B0_MAT1): Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1[1]. 6 (CT16B0_MAT0): Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0[1]. 7 (CT16B0_MAT1): Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1[1]. |
| EDGE | Edge control. This bit is significant only when the START field contains 010-111. 0 (RISING): Start conversion on a rising edge on the selected CAP/MAT signal. 1 (FALLING): Start conversion on a falling edge on the selected CAP/MAT signal. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |